// module name: Double_CTL
// author: yangtao2019
// date: 2021.07.12

`timescale 1ns / 1ps

module Double_CTL(
    input[3:0] funct3,
    output DoubleWd
);

    assign DoubleWd =   (funct3==3'b011)? 1'b1 :    // Double word operation
                        (funct3==3'b010)? 1'b0 :    // Word operation
                                          1'b1 ;    // default: Double word

endmodule